Logic Analyzer
Moe Babazadeh · 8 ch · loop 1 s
Start
Rate
500 kS/s
1 MS/s
2 MS/s
4 MS/s
10 MS/s
25 MS/s
50 MS/s
100 MS/s
Length
10 ms
50 ms
100 ms
250 ms
500 ms
1 s
2 s
Trigger
None: start now
D1 RX falls: a keystroke
D0 TX falls: the console talks
I²C start: SDA falls, SCL high
D7 CS falls: flash selected
SPI fault: SCLK high, CS high
Read as a page
Moe Babazadeh, CTO at Neuroject: a logic analyzer capture of a device that tells the story over its buses
1.00 ms
Fit
Trigger
Prev
UART TX frame
Next
Edge
Channels
Trigger
D0
TX
UART
D1
RX
UART
D2
SCL
I²C
D3
SDA
I²C
D4
SCLK
SPI
D5
MOSI
SPI
D6
MISO
SPI
D7
CS
SPI
A0
3V3
rail
★
Bonus 5 of 19
Logic Analyzer
★
Previous
Inference
★
Next
Minefield
Random theme
Dark mode